Since a generally used power MOS Field Effect Transistor (hereinafter, referred to as ‘MOSFET’) has input impedance higher than a bipolar transistor, it has a large power gain and a simple driving circuit. Also, since the power MOSFET is a uni-polar device, it does not have time delay generated due to accumulation or re-combination by minority carriers while the device is turned off. Therefore, the application of the power MOSFET has gradually been spread to a switching mode power supply, a lamp ballast, and a motor driving circuit. Usually, as such a power MOSFET, a double diffused MOSFET (DMOSFET) structure using a planar diffusion technology is widely used. A representative LDMOS transistor of the DMOSFET structure is disclosed in U.S. Pat. No. 4,300,150 issued to Sel Colak on Nov. 10, 1981. Also, technologies integrating the LDMOS transistor with a CMOS transistor and a bipolar transistor are reported in “A 1200 BiCMOS Technology and Its Application,” ISPSD 1991, pp. 322-327 by Vladimir Rumennik and “Recent Advances in Power Integrated Circuits with High Level Integration,” ISPSD 1994, pp. 343-348 by Stephen P. Robb.
Since a LDMOS device has a simple structure, it is very suitable for application to a VLSI process. However, it has been thought that LDMOS devices are poor in characteristics than a vertical DMOS (VDMOS) so that it has not sufficiently been spotlighted. While a reduced surface field (RESURF) LDMOS device has excellent on-resistance (Rsp), its structure is applicable to only devices of which source is grounded, and is very complicated and difficult in application.
As illustrated in example FIG. 1, LDMOS transistor device 10 is provided including first and second LDMOS transistors 10a and 10b and source region 16a and drain region 18a. LDMOS transistor 10a can be formed on and/or over silicon substrate 11 having a silicon-on-insulator (SOI) structure, buffer oxide 12 and semiconductor layer 14 covering silicon substrate 11. Herein, reference numbers 24a and 24b indicate insulating layers. N-type doped source region 16a is formed in P-type doped well region 20 such as P-type body. P-type body 20 may extend through the semiconductor layer 14 to an upper surface of buffer oxide 12 or exist only within the semiconductor layer 14. Drain region 18a is provided adjacent on one side of field insulating region 23a. Field insulating region 23a can be formed of a field oxide such as a thermally grown silicon oxide. Gate electrode 26a is formed on and/or over a surface of semiconductor layer 14 and extend from an upper surface of a portion of source region 16a to an upper surface of field insulating region 23a. Gate electrode 26a is composed of polysilicon doped with impurities. Gate electrode 26a is isolated from the surface of semiconductor 14 by gate insulating layer 28a. Gate insulating layer 28a can be formed of an oxide, or a nitride, or a compound thereof (i.e., a stacked NO or ONO layer). A sidewall region may be formed on and/or over a sidewall of gate electrode 26a. The sidewall region may be formed of an oxide such as a silicon oxide or a nitride such as a silicon nitride. High concentration doped body region 30 formed in P-type body 20 to have a good contact against P-type body 20. Body region 30 is doped at a concentration higher than P-type body 20. Source/drain contacts 32a and 34 are also included in transistor device 10a in order to electrically couple source/drain regions 16a and 18a to other components in a circuit via insulating layer 24a. Contact 34 is used for source regions 16a and 16b of both transistors 10a and lob. Such a representative structure is disclosed in U.S. Pat. No. 5,369,045 to Wia T. Ng. et al.
As illustrated in ex ample FIG. 2, a LDMOS device includes a transistor device, a body diode, and parasitic capacitance between a drain and a gate. The body diode is a diode created by junction of P-type body 20 and N-type semiconductor layer 14 as illustrated in example FIG. 1, and is intrinsic in the LDMOS. Such an LDMOS device should withstand a high voltage between a drain and a source in an off state and rapidly flow a large current between the drain and the source in an on state. Breakdown of the device occurs according to the high voltage between the drain and the source in the vicinity of a junction of gate insulating layer 28a or P-type body 20 and source regions 16a and 16b. In a case where the high voltage is continuously applied to gate insulating layer 28a, stress is accumulated on gate insulating layer 28a so that gate insulating layer 28a is broken down. Therefore, in a case where gate insulating layer 28a is formed relatively thick in order to improve its breakdown voltage characteristics, it acts as a factor deteriorating operation characteristics of the device due to the increase of threshold voltage.
As illustrated in example FIG. 3, in a case of driving inductor load through a push-pull structure or a bridge structure having DMOS devices m1 and m2, there is a forward conducting operation region of the body diode such as Im2, together with a backward conducting operation region of the body diode such as Im1 in example FIG. 2. If the current of the body diode is large, minority carriers are accumulated, diode off is delayed, and operation of a parasitic bipolar junction transistor is caused.